ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 115

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7FOXF1, ST7FOXK1, ST7FOXK2
Note:
Lite Timer Autoreload register (LTARR)
Reset value: 0000 0000 (00h)
Bits 7:0 = AR[7:0] Counter 2 Reload value
These bits register is read/write by software. The LTARR value is automatically loaded into
Counter 2 (LTCNTR) when an overflow occurs.
Lite Timer Counter 2 (LTCNTR)
Reset value: 0000 0000 (00h)
Bits 7:0 = CNT[7:0] Counter 2 Reload value
Lite Timer Control/status register (LTCSR1)
Reset value: 0x00 0000 (x0h)
Bit 7 = ICIE Interrupt Enable bit
Bit 6 = ICF Input Capture flag
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
CNT7
AR7
ICIE
This register is read by software. The LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
7
7
7
CNT6
AR6
ICF
CNT5
AR5
TB
TB1IE
CNT4
AR4
Read / Write
Read / Write
Read only
CNT3
TB1F
AR3
CNT2
AR2
On-chip peripherals
CNT1
AR1
CNT0
AR0
115/226
0
0
0