ST7FLITEU05B6 STMicroelectronics, ST7FLITEU05B6 Datasheet - Page 72
![MCU 8BIT SGL VOLT FLASH 8-DIP](/photos/1/39/13944/497-8-dip_sml.jpg)
ST7FLITEU05B6
Manufacturer Part Number
ST7FLITEU05B6
Description
MCU 8BIT SGL VOLT FLASH 8-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITEU05M6.pdf
(139 pages)
Specifications of ST7FLITEU05B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ST7FLITEUx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ICC
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
On-chip peripherals
11.1.7
Note:
72/139
Register description
Lite timer control/status register (LTCSR)
Reset Value: 0000 0x00 (0xh)
Bit 7 = ICIE Interrupt Enable.
Bit 6 = ICF Input Capture Flag.
After an MCU reset, software must initialise the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection.
Bit 4 = TBIE Timebase Interrupt enable.
Bit 3 = TBF Timebase Interrupt Flag.
Bit 2 = WDGRF Force Reset/ Reset Status Flag
ICIE
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
This bit is used in two ways: it is set by software to force a watchdog reset. It is set by
hardware when a watchdog reset occurs and cleared by hardware or by software. It is
cleared by hardware only when an LVD reset occurs. It can be cleared by software after
a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
7
ICF
TB
OSC
OSC
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
TBIE
Read / Write
TBF
WDGR
ST7LITEU05 ST7LITEU09
WDGE
WDGD
0