ST7FLITEU05B6 STMicroelectronics, ST7FLITEU05B6 Datasheet - Page 78
![MCU 8BIT SGL VOLT FLASH 8-DIP](/photos/1/39/13944/497-8-dip_sml.jpg)
ST7FLITEU05B6
Manufacturer Part Number
ST7FLITEU05B6
Description
MCU 8BIT SGL VOLT FLASH 8-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITEU05M6.pdf
(139 pages)
Specifications of ST7FLITEU05B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ST7FLITEUx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ICC
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
On-chip peripherals
Caution:
78/139
Bit 2 = OVF Overflow flag.
When set, the OVF bit stays high for 1 f
selection) after it has been cleared by software.
Bit 1 = OVFIE Overflow interrupt enable.
Bit 0 = CMPIE Compare interrupt enable.
Counter register high (CNTRH)
Reset Value: 0000 0000 (00h)
Counter register low (CNTRL)
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
CN7
15
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
This bit is read/write by software and clear by hardware after a reset. It allows to mask
the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTRH can be incremented between the two read operations and to have an accurate
result when f
are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR register.
0
7
CN6
0
timer
= f
CPU
CN5
0
, special care must be taken when CNTRL values close to FFh
CN4
COUNTER
0
Read only
Read only
cycle (up to 1ms depending on the clock
CN11
CN3
CN10
CN2
ST7LITEU05 ST7LITEU09
CN9
CN1
CN8
CN0
8
0