ST7FLITEU05M3TR STMicroelectronics, ST7FLITEU05M3TR Datasheet - Page 52

• Manufacturer Part Number: ST7FLITEU05M3TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Power saving modes
9.3
Note:
52/139
1
Figure 23. Slow mode clock transition
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up. Refer to
Figure 24. Wait mode flowchart
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC
register is set during the interrupt routine and cleared when the CC register is popped.
Figure
24.
WFI INSTRUCTION
N
f
SMS
CPU
f
OSC
INTERRUPT
Y
OR SERVICE INTERRUPT
FETCH RESET VECTOR
256 OR 512 CPU CLOCK
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
f
OSC
NORMAL RUN MODE
CYCLE
/32
RESET
REQUEST
Y
DELAY
f
OSC
OFF
OFF
X
ON
ON
ON
ON
ON
ON
ON
0
0
1)
ST7LITEU05 ST7LITEU09