Z8F0113PJ005SG Zilog, Z8F0113PJ005SG Datasheet - Page 14
Z8F0113PJ005SG
Manufacturer Part Number
Z8F0113PJ005SG
Description
IC ENCORE MCU FLASH 1K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0223SB005SG.pdf
(247 pages)
Specifications of Z8F0113PJ005SG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-3995
Z8F0113PJ005SG
Z8F0113PJ005SG
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CPU and Peripheral Overview
PS024314-0308
eZ8 CPU Features
General-Purpose I/O
Flash Controller
The eZ8 CPU, Zilog’s latest 8-bit central processing unit (CPU), meets the continuing
demand for faster and code-efficient microcontrollers. The eZ8 CPU executes a superset
of the original Z8
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For more information on eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) avail-
able for download at www.zilog.com.
Z8 Encore! XP F0823 Series features 6 to 24 port pins (Ports A–C) for general-purpose
I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is
individually programmable. 5 V tolerant input pins are available on all I/Os on 8-pin
devices, most I/Os on other package types.
The Flash Controller programs and erases Flash memory. The Flash Controller supports
protection against accidental program and erasure, as well as factory serialization and read
protection.
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory.
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks.
Compatible with existing Z8 code.
Expanded internal Register File allows access of up to 4 KB.
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C.
Pipelined instruction fetch and execution.
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL.
New instructions support 12-bit linear addressing of the Register file.
Up to 10 MIPS operation.
C-Compiler friendly.
2 to 9 clock cycles per instruction.
®
instruction set. The eZ8 CPU features include:
Z8 Encore! XP
Product Specification
®
F0823 Series
Overview
4
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