Z8F0113PJ005SG Zilog, Z8F0113PJ005SG Datasheet - Page 176
Z8F0113PJ005SG
Manufacturer Part Number
Z8F0113PJ005SG
Description
IC ENCORE MCU FLASH 1K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0223SB005SG.pdf
(247 pages)
Specifications of Z8F0113PJ005SG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-3995
Z8F0113PJ005SG
Z8F0113PJ005SG
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PS024314-0308
Caution:
Clock Failure Detection and Recovery
OSC Control Register Unlocking/Locking
To write the oscillator control register, unlock it by making two writes to the OSCCTL
register with the values
changes the value of the actual register and returns the register to a locked state. Any other
sequence of oscillator control register writes has no effect. The values written to unlock
the register must be ordered correctly, but are not necessarily consecutive. It is possible to
write to or read from other registers within the unlocking/locking operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a
different oscillator, it is appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Primary Oscillator Failure
Z8 Encore! XP
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be deasserted in
the OSCCTL register).
Unintentional accesses to the oscillator control register can actually stop the chip by
switching to a non-functioning oscillator. To prevent this condition, the oscillator con-
trol block employs a register unlocking/locking scheme.
®
F0823 Series devices can generate non-maskable interrupt-like events
E7H
followed by
18H
. A third write to the OSCCTL register
Watchdog Timer
Z8 Encore! XP
on page 87.
Product Specification
®
Oscillator Control
F0823 Series
166
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