ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 155

• Manufacturer Part Number: ST7FLITE39F2M3TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 100. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
OSC
t
t
w(SCKH)
w(SCKL)
Symbol
1/t
t
t
t
t
t
t
dis(SO)
t
su(SS)
t
t
t
su(MI)
su(SI)
t
t
t
h(SS)
t
v(MO)
h(MO)
f
a(SO)
v(SO)
h(SO)
h(MI)
r(SCK)
h(SI)
SCK =
f(SCK)
MISO
MOSI
c(SCK)
, and T
1)
SS
1)
1)
1)
1)
1)
1)
1)
1)
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
1)
OUTPUT
INPUT
1)
1)
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
a(SO)
t
su(SS)
Parameter
t
su(SI)
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
= 8 MHz, then T
t
t
h(SI)
c(SCK)
t
DD
Master
f
Slave
f
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable
edge)
v(SO)
CPU
CPU
DD
,
=8MHz
=8MHz
BIT6 OUT
CPU
and 0.7xV
Conditions
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
= 1 / f
3)
CPU
DD
BIT1 IN
.
= 125ns and t
t
h(SO)
(4 x T
f
CPU
t
t
r(SCK)
f(SCK)
0.0625
see I/O port pin description
0.25
0.25
su(SS)
Min
CPU
120
100
100
100
100
100
90
/128 =
0
0
0
) + 50
LSB IN
= 550ns.
LSB OUT
t
h(SS)
f
f
ST7LITE3xF2
CPU
CPU
Max
120
240
120
2
4
/4 =
/2 =
t
dis(SO)
155/173
t
Unit
MHz
note 2
CPU
see
ns