ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 48
ST7FOXK1T6
Manufacturer Part Number
ST7FOXK1T6
Description
IC MCU 8BIT 1V FLASH MEM 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FOXF1M6.pdf
(226 pages)
Specifications of ST7FOXK1T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FOXx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 1 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-6336
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FOXK1T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST7FOXK1T6TR
Manufacturer:
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10 000
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Supply, reset and clock management
6.5.4
48/226
RC Control Register Low (RCCRL)
Reset value: 011x 0x00 (xxh)
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the
LVDRF flags areis used to select the reset source (see
page
Table 10.
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
Bits 1:0 = Reserved, must be kept cleared
0
7
These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately
after reset to adjust the RC oscillator frequency. Refer to
oscillator on page
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
48).
CR1
Reset source selection
External RESET pin
CR0
RESET source
34.
Watchdog
LVD
WDGRF
Read/write
0
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 10: Reset source selection on
LVDRF
LVDRF
Section 6.1.1: Internal RC
0
0
1
0
WDGRF
X
0
1
0
0
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