Z8F0412SJ020SG Zilog, Z8F0412SJ020SG Datasheet - Page 153

• Manufacturer Part Number: Z8F0412SJ020SG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0412SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4107; Z8F0412SJ020SG

Table 71. I
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
I
Caution:
2
C Status Register
2
C Status Register (I2CSTAT)
TDRE
7
1
The Read-only I
TDRE—Transmit Data Register Empty
When the I
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit is cleared by reading the I
execution of the OCD’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
10B—10-Bit Address
This bit indicates whether a 10-bit or 7-bit address is being transmitted. After the START
bit is set, if the five most-significant bits of the address are
set, it is reset once the first byte of the address has been sent.
because software cannot tell when the bit is updated by hardware. In the case of write
transactions, the I 2 C pauses at the beginning of the Acknowledge cycle if the next
transmit data or address byte has not been written (TDRE = 1) and STOP and START
= 0. In this case the ACK bit is not updated until the transmit interrupt is serviced and
the Acknowledge cycle for the previous byte completes. For examples on usage of the
ACK bit, see
Only Transaction with a 10-bit Address
Software must be cautious in making decisions based on this bit within a transaction
RDRF
2
6
C Controller is enabled, this bit is 1 when the I
2
Address Only Transaction with a 7-bit Address
C Status register
ACK
5
2
C Controller is enabled and the I
10B
2
(Table
C Data Register (unless the read is performed using
4
F51H
R
71) indicates the status of the I
on page 133.
RD
3
0
2
C Controller to generate an interrupt.
Z8 Encore! XP
TAS
2
11110B
2
C Data Register is empty.
2
C Controller has received a
Product Specification
on page 131 and
, this bit is set. When
DSS
1
2
®
C Controller.
F0822 Series
I2C Controller
NCKI
Address
2
0
C
140