ST7FLITE35M6TR STMicroelectronics, ST7FLITE35M6TR Datasheet
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ST7FLITE35M6TR
Specifications of ST7FLITE35M6TR
Related parts for ST7FLITE35M6TR
ST7FLITE35M6TR Summary of contents
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MCU with single voltage Flash, data EEPROM, ADC, timers, Features Memories ■ – 8 Kbytes program memory: single voltage ex- tended Flash (XFlash) Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP), data retention: 20 ...
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ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LINSCI LIMITATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION The ST7LITE3 is a member of the ST7 microcon- troller family. All ST7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST7LITE3 features FLASH memory with byte-by-byte In-Circuit Programming ...
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ST7LITE3xF2 2 PIN DESCRIPTION Figure 2. 20-Pin QFN Package Pinout RESET SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 Figure 3. 20-Pin SO and DIP Package Pinout SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 RDI/AIN6/PB6 6/173 ...
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PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Type input output supply In/Output level CMOS 0.3V T Output level 20mA high sink (on N-buffer only) Port and control configuration: – Input: ...
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ST7LITE3xF2 Level Pin Name PA6 /MCO ICCCLK/ I/O BREAK PA5 /ATPWM3 I/O C ICCDATA 12 14 PA4/ATPWM2 I PA3/ATPWM1 I PA2/ATPWM0 I PA1/ATIC I ...
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REGISTER & MEMORY MAP As shown in Figure 4, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 ...
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ST7LITE3xF2 Table 3. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h 0007h 0008h LTCSR2 0009h LTARR LITE 000Ah LTCNTR TIMER 2 000Bh LTCSR1 000Ch ...
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Register Address Block Label 0031h SPIDR 0032h SPI SPICR 0033h SPICSR 0034h ADCCSR 0035h ADC ADCDRH 0036h ADCDRL 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR 003Bh 003Ch ITC EISR 003Dh to 003Fh 0040h SCISR ...
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ST7LITE3xF2 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices ...
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FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC INTERFACE ICP needs a minimum of 4 and pins to be connected to the programming tool. These pins are: – RESET: device reset – device power supply ground SS ...
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ST7LITE3xF2 FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a pro- ...
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DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 6. EEPROM Block ...
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ST7LITE3xF2 DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 7 describes these different memory access modes. Read ...
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DATA EEPROM (Cont’d) 2 Figure 8. Data E PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 PHASE 1 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle ...
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ST7LITE3xF2 DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter ...
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DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This ...
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ST7LITE3xF2 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing ...
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CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST7LITE3xF2 MCU Reset, or after a Reset Stack Pointer instruc- tion (RSP), the Stack Pointer contains its reset val- ue (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features Clock ...
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ST7LITE3xF2 If both the RC oscillator and the PLL are disabled driven by the external clock. OSC Figure 12. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. t LOCK t STARTUP When the PLL ...
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Figure 13. Clock Management Block Diagram CR9 CR8 CR7 CR6 Tunable 1% RC Oscillator OSCRANGE[2:0] Option bits CLKIN CLKIN f DIVIDER CLKIN CLKIN CLKIN/ OSC1 OSC OSC2 1-16 MHZ or 32kHz f OSC /32 DIVIDER /32 DIVIDER RCCR CR5 CR4 ...
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ST7LITE3xF2 7.4 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block (1 to 16MHz or 32kHz): an external source ■ 5 crystal or ceramic resonator oscillators ■ ...
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RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ Note: A reset can ...
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ST7LITE3xF2 Figure 15. Reset Block Diagram V DD RESET Note 1: See “Illegal Opcode Reset” on page 128. for more details on illegal opcode reset conditions. 28/173 Filter PULSE GENERATOR INTERNAL RESET WATCHDOG RESET 1) ILLEGAL OPCODE ...
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RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 7.5.3 External Power-On ...
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ST7LITE3xF2 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the ...
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Figure 18. Reset and Supply Management Block Diagram RESET SEQUENCE RESET MANAGER (RSM WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT SICSR WDGRF AUXILIARY VOLTAGE ST7LITE3xF2 STATUS FLAG AVD Interrupt Request LOCKED LVDRF AVDF AVDIE LOW VOLTAGE DETECTOR ...
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ST7LITE3xF2 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply voltage (V ). The V AVD IT-(AVD) for ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. The SICSR register is frozen. The AVD becomes inactive and the AVD in- HALT terrupt ...
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ST7LITE3xF2 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0110 0xx0 (6xh) 7 WDG 0 CR1 CR0 LOCKED LVDRF AVDF AVDIE RF Bit 7 = Reserved, must be kept cleared. Bits 6:5 ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...
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ST7LITE3xF2 INTERRUPTS (cont’d) Figure 20. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 6. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 AWU 7 Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 ...
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INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 7. Bit ...
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ST7LITE3xF2 INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection ...
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POWER SAVING MODES 9.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the ST7 (see Figure 21): Slow ■ Wait (and ...
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ST7LITE3xF2 POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During ...
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POWER SAVING MODES (Cont’d) 9.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when ACTIVE-HALT is disabled (see section 9.5 on page 42 for more details) ...
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ST7LITE3xF2 POWER SAVING MODES (Cont’d) 9.4.0.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding ...
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POWER SAVING MODES (Cont’d) Figure 26. ACTIVE-HALT Timing Overview ACTIVE 256 OR 4096 CPU HALT RUN CYCLE DELAY RESET OR HALT INTERRUPT INSTRUCTION [Active Halt Enabled] Figure 27. ACTIVE-HALT Mode Flow-chart OSCILLATOR PERIPHERALS HALT INSTRUCTION CPU (Active Halt enabled) I ...
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ST7LITE3xF2 POWER SAVING MODES (Cont’d) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: – The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a ...
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POWER SAVING MODES (Cont’d) Figure 30. AWUFH Mode Flow-chart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE 0 1) WDGHALT 1 AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS CPU I[1:0] BITS INTERRUPT AWU RC OSC MAIN OSC Y ...
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ST7LITE3xF2 POWER SAVING MODES (Cont’d) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h AWUF AWUM AWUEN Bits 7:3 = Reserved. Bit 1= AWUF Auto Wake Up Flag This bit ...
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I/O PORTS 10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have ...
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ST7LITE3xF2 I/O PORTS (Cont’d) Figure 31. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS From on-chip periphera ALTERNATE ENABLE BIT DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL Combinational INTERRUPT REQUEST (ei ) ...
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I/O PORTS (Cont’d) Table 10. I/O Configurations V PAD V PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate ...
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ST7LITE3xF2 I/O PORTS (Cont’d) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, ...
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I/O PORTS (Cont’d) The I/O port register configurations are summa- rised as follows. Standard Ports PA7:0, PB6:0 MODE floating input pull-up input open drain output push-pull output Table 11. Port Configuration (Standard ports) Port Pin name Port A PA7:0 Port ...
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ST7LITE3xF2 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application ...
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WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: it counts down even if the watchdog is disabled. The value ...
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ST7LITE3xF2 WATCHDOG TIMER (Cont’d) 11.1.5 Interrupts None. 11.1.6 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared ...
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WATCHDOG TIMER (Cont’d) Table 15. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) WDGCR WDGA 002Eh Reset Value ST7LITE3xF2 ...
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ST7LITE3xF2 11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for gen- eral-purpose timing functions based on one or two free-running 12-bit upcounters with an input capture register and four PWM ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Figure 35. Dual Timer Mode (ENCNTR2=1) ATIC Edge Detection Circuit 12-Bit Autoreload Register 1 12-Bit Upcounter 1 Clock Control 12-Bit Upcounter 2 12-Bit Autoreload Register 2 12-bit Input Capture Output Compare PWM0 Duty Cycle ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) 11.2.3 Functional Description 11.2.3.1 PWM Mode This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins. PWM Frequency The four PWM signals can have ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Figure 37. PWM Function 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) 000 WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 Figure 38. PWM Signal from 0% to 100% Duty Cycle f COUNTER COUNTER ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Dead Time Generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The non-overlapping PWM0/ ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Break Function The break function can be used to perform an emergency shutdown of the application being driv the PWM signals. The break function is activated by the external BREAK pin (active ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) 11.2.3.2 Output Compare Mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter (CNTR1) reaches the value stored in the Active DCRxH and ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) 11.2.3.3 Input Capture Mode The 12-bit ATICR register is used to latch the val the 12-bit free running upcounter CNTR1 af- ter a rising or falling edge is detected on the ATIC ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Long input capture ■ Pulses that last between 8µs and 2s can be meas- ured with an accuracy of 4µ following conditions: – The 12-bit AT3 Timer is clocked by the ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) – At the second input capture on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: LTICR = LT2 ATICRH = ATH2 Figure 45. Long ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) 11.2.5 Interrupts Enable Exit Interrupt Event Control from 1) Event Flag Bit WAIT Overflow OVF1 OVIE1 Event AT3 IC ICF ICIE Event CMP Event CMPFx CMPIE Note 1: The CMP and AT3 IC ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h ICF ICIE CK1 CK0 Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) AUTORELOAD REGISTER (ATR1H) Read / Write Reset Value: 0000 0000 (00h ATR11 ATR10 ATR9 AUTORELOAD REGISTER (ATR1L) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 ATR6 ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bit 3:0 = PWM[3:0] Break Pattern. These ...
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ST7LITE3xF2 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Bit 4 = OVFIE2 Overflow interrupt 2 enable This bit is read/write by software and controls the overflow interrupt of counter2. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled. Bit 3 = OVF2 ...
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Table 16. Register Map and Reset Values Address Register 7 Label (Hex.) ATCSR 0D 0 Reset Value CNTR1H 0E 0 Reset Value CNTR1L CNTR1_7 0F Reset Value 0 ATR1H 10 0 Reset Value ATR1L ...
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ST7LITE3xF2 Address Register 7 Label (Hex.) ATCSR2 21 0 Reset Value BREAKCR 22 0 Reset Value ATR2H 23 0 Reset Value ATR2L ATR7 24 Reset Value 0 DTE DTGR 25 Reset Value 0 72/173 ICS OVFIE2 ...
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LITE TIMER 2 (LT2) 11.3.1 Introduction The Lite Timer can be used for general-purpose timing functions based on two free-running 8- bit upcounters and an 8-bit input capture register. 11.3.2 Main Features Realtime Clock (RTC) ■ – ...
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ST7LITE3xF2 LITE TIMER (Cont’d) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f overflow event ...
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LITE TIMER (Cont’d) 11.3.4 Low Power Modes Mode Description No effect on Lite timer SLOW (this peripheral is driven directly by f /32) OSC WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops ...
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ST7LITE3xF2 LITE TIMER (Cont’d) LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) 7 CNT7 CNT7 CNT7 CNT7 CNT3 Bits 7:0 = CNT[7:0] Counter 2 Reload Value. This register is read by software. The LTARR val- ue ...
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LITE TIMER (Cont’d) Table 17. Lite Timer Register Map and Reset Values Address Register 7 Label (Hex.) LTCSR2 08 0 Reset Value LTARR AR7 09 Reset Value 0 LTCNTR CNT7 0A Reset Value 0 LTCSR1 ICIE 0B Reset Value 0 ...
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ST7LITE3xF2 ON-CHIP PERIPHERALS (cont’d) 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a ...
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SERIAL PERIPHERAL INTERFACE (SPI) (cont’d) Figure 48. Serial Peripheral Interface Block Diagram SPIDR MOSI MISO 8-bit Shift Register SOD bit SCK SS Data/Address Bus Read Read Buffer 7 SPIF WCOL Write SPIE MASTER CONTROL SERIAL CLOCK GENERATOR ST7LITE3xF2 Interrupt request ...
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ST7LITE3xF2 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 49. The MOSI pins are connected together and the MISO pins are connected together. In ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST7LITE3xF2 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 52). Note: The idle state of SCK must correspond to the polarity selected ...
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ST7LITE3xF2 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master de- vice’s SS pin is pulled low. When a Master mode fault occurs: – The MODF bit is set and ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured using a device as the master and ...
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ST7LITE3xF2 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ...
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Register Description SPI CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 7 = SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by software. 0: Interrupt is ...
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ST7LITE3xF2 SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF - Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is set ...
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Table 19. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0031h Reset Value SPICR SPIE 0032h Reset Value SPICSR SPIF 0033h Reset Value SPE SPR2 MSTR WCOL ...
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ST7LITE3xF2 11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) 11.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d) 11.5.4 General Description The interface is externally connected to another device by two pins: – TDO: Transmit Data Output. When the transmit- ter is disabled, the output pin returns to its I/O port configuration. When ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 55. SCI Block Diagram (in Conventional Baud Rate Generator Mode) Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL SCICR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.5 SCI Mode - Functional Description Conventional Baud Rate Generator Mode The block diagram of the Serial Control Interface in conventional baud rate generator mode is shown in Figure 55. It uses four ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.5.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.5.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.5.4 Conventional Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (16 PR) TR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 57. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.5.6 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.6 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 11.5.8 SCI Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty This bit ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE PCE 1) This bit has a different function in LIN mode, please refer to the LIN mode ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE 1) This bit has a different function in LIN mode, please refer to the LIN mode ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) 7 SCP1 SCP0 SCT2 SCT1 SCT0 Note: When LIN slave mode is disabled, the SCI- BRR register controls the conventional baud rate generator. ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) 7 ERPR ERPR ERPR ERPR ERPR Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) 11.5.9 LIN Mode - Functional Description. The block diagram of the Serial Control Interface, in LIN slave mode is shown in It uses six registers: – 3 control registers: SCICR1, SCICR2 and SCICR3 – ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 58. LIN Characters 8-bit Word length (M bit is reset) Data Character Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Idle Line LIN Synch Field Start Bit0 Bit1 Bit2 ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 59. SCI Block Diagram in LIN Slave Mode Transmit Data Register (TDR) TDO RDI TRANSMIT SCICR2 TIE TCIE SCI INTERRUPT CONTROL f CPU LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION SCIBRR LPR7 f ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.9.3 LIN Reception In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features for han- dling the LIN Header automatically (identifier de- ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.9.4 LIN Error Detection LIN Header Error Flag The LIN Header Error Flag indicates that an invalid LIN Header has been detected. When a LIN Header Error occurs: – The LHE flag is ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) If LHE bit is set due to this error during Fields other than LIN Synch Field or if LASE bit is reset then the current received Header is discarded and the SCI ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.9.5 LIN Baud Rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic Resynchronization To automatically adjust the baud rate ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 62. LDIV Read / Write Operations When LDUM = 0 Write LPFR Write LPR MANT(7:0) MANT(7:0) Read LPR Figure 63. LDIV Read / Write Operations When LDUM = 1 Write LPFR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.9.7 LINSCI Clock Tolerance LINSCI Clock Tolerance when unsynchronized When LIN slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the LINSCI clock ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.9.9 Error due to LIN Synch measurement The LIN Synch Field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 11.5.10 LIN Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE LHE Bits 7:4 = Same function as in SCI mode; please refer to ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bits 7:2 Same function as in SCI mode; please re- fer to Section 11.5.8 SCI Mode ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) SCICR2 register is set, the LHDM bit selects the Wake-Up method (replacing the WAKE bit). 0: LIN Synch Break Detection Method 1: LIN Identifier Field Detection Method Bit 2 = LHIE LIN Header ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN PRESCALER FRACTION REGISTER (LPFR) Read/Write Reset Value: 0000 0000 (00h) 7 LPFR Bits 7:4 = Reserved. Bits 3:0 = LPFR[3:0] Fraction of LDIV These 4 bits ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN HEADER LENGTH REGISTER (LHLR) Read Only Reset Value: 0000 0000 (00h). 7 LHL7 LHL6 LHL5 LHL4 LHL3 Note: In LIN Slave mode when LASE = 1 or LHDM = 1, the LHLR ...
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ST7LITE3xF2 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (Cont’d) Table 21. LINSCI1 Register Map and Reset Values Addr. Register Name (Hex.) SCISR 40 Reset Value SCIDR 41 Reset Value SCIBRR 42 LPR (LIN Slave Mode) Reset Value SCICR1 43 Reset Value ...
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A/D CONVERTER (ADC) 11.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST7LITE3xF2 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input ...
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A/D CONVERTER (ADC) (Cont’d) 11.6.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 0 Bit 7 = EOC End of Conversion This bit is set by ...
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ST7LITE3xF2 Table 22. ADC Register Map and Reset Values Address Register Label (Hex.) ADCCSR EOC 0034h Reset Value ADCDRH 0035h Reset Value ADCDRL 0036h Reset Value 124/173 SPEED ADON ...
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INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative ...
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ST7LITE3xF2 ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait ...
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ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST7LITE3xF2 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift ...
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INSTRUCTION GROUPS (cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...
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ST7LITE3xF2 INSTRUCTION GROUPS (cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST7LITE3xF2 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics ...
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OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices T = -40 to +125°C unless otherwise specified. A Symbol Parameter V Supply voltage DD External clock frequency on f CLKIN CLKIN pin Figure 69. f Maximum Operating Frequency Versus ...
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ST7LITE3xF2 OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables. 13.3.1.1 Devices tested for T Symbol Parameter Internal RC oscillator frequency Accuracy of Internal RC ACC oscillator with RC ...
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OPERATING CONDITIONS (Cont’d) Figure 70. Typical accuracy with RCCR=RCCR0 vs V 3.00% 2.50% 2.00% 1.50% 1.00% 0.50% 0.00% -0.50% -1.00% 4.5 Figure 71. Typical RCCR0 vs V 1.1 1.05 1 0.95 0.9 2.7 2.9 3.1 3.3 3.5 = 4.5 to ...
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ST7LITE3xF2 OPERATING CONDITIONS (Cont’d) 13.3.1.2 Devices with tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of Internal RC ACC oscillator when calibrated RC with RCCR=RCCR1 RC oscillator current con- I DD(RC) sumption t RC ...
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OPERATING CONDITIONS (Cont’d) Figure 72. Typical accuracy with RCCR=RCCR1 vs V 1.50% 1.00% 0.50% 0.00% -0.50% -1.00% Figure 73. Typical RCCR1 vs V 1.1 1.05 1 0.95 0.9 2.7 2.9 3.1 3.3 = 3-3.6V and Temperature DD 3 3.3 VDD ...
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ST7LITE3xF2 OPERATING CONDITIONS (Cont’d) Figure 74. PLL ∆f /f versus time CPU CPU ∆f /f CPU CPU Max 0 Min Figure 75. PLLx4 Output vs CLKIN frequency 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 2 External Input Clock ...
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Operating Conditions with Low Voltage Detector (LVD -40 to 125°C, unless otherwise specified A Symbol Parameter Reset release threshold V (LVD) IT+ (V rise) DD Reset generation threshold V (LVD) IT- (V fall LVD voltage ...
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ST7LITE3xF2 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 13.4.1 Supply Current T = ...
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LVD disabled. 3. SLOW mode selected with f CPU V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled SLOW-WAIT mode selected with f V ...
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ST7LITE3xF2 SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 79. Typical I in WAIT vs 8MHz 2.5 4MHz 2.0 1MHz 1.5 1.0 0.5 0.0 2.4 2.7 3.3 Vdd (V) Figure 80. Typical I in SLOW-WAIT vs 8MHz 800.00 700.00 ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External Clock Source Symbol V ...
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ST7LITE3xF2 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, ...
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MEMORY CHARACTERISTICS T = -40°C to 125°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter V Operating voltage for Flash write/erase DD Programming time for ...
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ST7LITE3xF2 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the ...
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... Static latch-up class Note: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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ST7LITE3xF2 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V 1) hys hysteresis I Input leakage ...
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Figure 85. Typical I vs Ta=140°C 80 Ta=95°C 70 Ta=25°C Ta=-45 ° CHARACTERIZED 2.5 3 3.5 4 4.5 Vdd(V) with ...
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ST7LITE3xF2 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 88) 1) ...
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Figure 86. Typical 4.0 3.5 -45°C 25°C 3.0 90°C 2.5 110°C 130°C 2.0 1.5 1.0 0.5 0.0 0. lio (mA) Figure 87. Typical 1.2 -45°C 1.0 25°C ...
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ST7LITE3xF2 Figure 94. Typical 1.8 1.6 -45°C 25°C 1.4 90°C 1.2 110°C 1.0 130°C 0.8 0.6 0.4 0.2 0.0 -0. lio (mA) Figure 96. Typical V vs 0.4 0.3 0.3 0.2 ...
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CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 125°C, unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low ...
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ST7LITE3xF2 CONTROL PIN CHARACTERISTICS (Cont’d) Figure 98. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01mF Figure 99. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01µF Required Note 1: – The reset network protects ...
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COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK = SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock ...
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ST7LITE3xF2 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 101. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 102. SPI ...
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ADC CHARACTERISTICS Subject to general operating condition for V Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC ...
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ST7LITE3xF2 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with 3V V ≤ DD ≤ Symbol Parameter |E | Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity ...
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PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level in- terconnect. The category of second Level Inter- connect is marked on the ...
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ST7LITE3xF2 Figure 107. 20-Pin Plastic Dual In-Line Package, 300-mil Width 14.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance R thJA (junction to ambient) T Maximum junction temperature Jmax P Maximum power dissipation Dmax Notes: The ...
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DEVICE CONFIGURATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST7PLITE3 devices are Factory Advanced Serv- ice Technique ROM (FASTROM) versions: they are factory programmed FLASH devices. ...
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ST7LITE3xF2 OPTION BYTES (Cont’d) OPTION BYTE 0 7 OSCRANGE AWU CK 2:0 Default Value OPTION BYTE 1 OPT 7 = PLLx4x8 PLL Factor Selection. 0: PLLx4 1: PLLx8 OPT 6 = PLLOFF PLL Disable This option ...
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... ST Sales Office nearest to you. ing the correctly completed OPTION LIST append page 164. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. ST7 F LITE3x F ST7LITE3xF2 ...
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... Reference FASTROM Code *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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... DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. ...
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ST7LITE3xF2 15.4 ST7 APPLICATION NOTES Table 27. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION ...
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Table 27. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK ...
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ST7LITE3xF2 Table 27. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 USING ...
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KNOWN LIMITATIONS 16.1 CLEARING ACTIVE OUTSIDE INTERRUPT ROUTINE When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context The symptom ...
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ST7LITE3xF2 IMPORTANT NOTES (Cont’d) Impact on application Software may execute the interrupt routine twice after header reception. Moreover, in reception mode, as the receiver is no longer in mute mode, an interrupt will be generat each data byte ...
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REVISION HISTORY Date Revision 29-Jul-05 4 First release on Internet Added QFN20 package In Table 3, “Hardware Register Map,” on page 10, replaced for LTCSR1, ATCSR and SICSR reset values section 4.4 on page 13 Modified ...
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ST7LITE3xF2 Removed note “negative injection not allowed on PB0 and PB1 pins” section 13.2.2 on page Added QFN20 package pinout (with new QFN20 mechanical data): 07-Nov-06 7 Figure 105 on page 159 Modified Modified option list on Added note 1 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...