ST7FLITE35M6TR STMicroelectronics, ST7FLITE35M6TR Datasheet - Page 147
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ST7FLITE35M6TR
Manufacturer Part Number
ST7FLITE35M6TR
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE35F2M6TR.pdf
(173 pages)
Specifications of ST7FLITE35M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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EMC CHARACTERISTICS (Cont’d)
13.7.2 EMI (Electromagnetic Interference)
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Note:
1. Data based on characterization results, not tested in production.
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity.
13.7.3.1 Electrostatic Discharge (ESD)
Electrostatic discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
ESD Absolute Maximum Ratings
Notes:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static latch-up
Two complementary static tests are required on 10
parts to assess the latch-up performance.
Electrical Sensitivities
Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
Symbol
V
Symbol
Symbol
ESD(HBM)
S
EMI
LU
Peak level
Electro-static discharge voltage
(Human Body Model)
Static latch-up class
Parameter
Parameter
Ratings
V
SO20 package,
conforming to SAE J 1752/3
DD
=5V, T
Conditions
A
=+25°C,
T
T
A
A
=+25°C
=+25°C
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard. For
more details, refer to the application note AN1181.
A supply overvoltage (applied to each power sup-
ply pin) and a current injection (applied to each in-
put, output and configurable I/O pin) are per-
formed on each sample. These tests are compliant
with the EIA/JESD 78 IC latch-up standard.
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
Frequency Band
Conditions
Conditions
Monitored
Max vs. [f
8/4MHz
16
20
15
Maximum value
3
OSC
6000
16/8MHz
ST7LITE3xF2
Class
3.5
/f
17
25
16
CPU
A
1)
]
1)
147/173
dBµV
Unit
Unit
-
V
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