ST7FLITE49K2B6 STMicroelectronics, ST7FLITE49K2B6 Datasheet - Page 168
![IC MCU 8BIT 8K FLASH 32DIP](/photos/7/4/70414/497-32-sdip_series_sml.jpg)
ST7FLITE49K2B6
Manufacturer Part Number
ST7FLITE49K2B6
Description
IC MCU 8BIT 8K FLASH 32DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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On-chip peripherals
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SPI control/status register (SPICSR)
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF Serial peripheral data transfer flag (Read only).
Bit 6 = WCOL Write collision status (Read only).
Bit 5 = OVR SPI overrun error (Read only).
Bit 4 = MODF Mode fault flag (Read only).
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI output disable.
SPIF
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see Figure 75).
0: No write collision occurred
1: A write collision has been detected
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See Section Overrun
condition (OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR
bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see Section
Master mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the
SPICR register. This bit is cleared by a software sequence (An access to the SPICSR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
7
WCOL
OVR
Read / Write (some bits Read only)
MODF
-
SOD
SSM
ST7LITE49K2
SSI
0
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