ST7FLITE49K2B6 STMicroelectronics, ST7FLITE49K2B6 Datasheet - Page 78
![IC MCU 8BIT 8K FLASH 32DIP](/photos/7/4/70414/497-32-sdip_series_sml.jpg)
ST7FLITE49K2B6
Manufacturer Part Number
ST7FLITE49K2B6
Description
IC MCU 8BIT 8K FLASH 32DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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I/O ports
10.2.4
Caution:
10.3
10.4
10.5
78/245
Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.
The analog input voltage level must be within the limits stated in the absolute maximum
ratings.
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
Figure 35. Interrupt I/O port state transitions
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to
pin
Low power modes
Table 26.
s
characteristics.
Mode
Wait
Halt
Effect of low power modes on I/O ports
No effect on I/O ports. External interrupts cause the device to exit from Wait
No effect on I/O ports. External interrupts cause the device to exit from Halt
floating/pull-up
interrupt
INPUT
01
(reset state)
floating
INPUT
00
open-drain
OUTPUT
XX
Description
10
mode.
mode.
= DDR, OR
OUTPUT
push-pull
11
Section 13.9: I/O port
ST7LITE49K2
Figure
35.
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