ST7FLITE49K2B6 STMicroelectronics, ST7FLITE49K2B6 Datasheet - Page 97
![IC MCU 8BIT 8K FLASH 32DIP](/photos/7/4/70414/497-32-sdip_series_sml.jpg)
ST7FLITE49K2B6
Manufacturer Part Number
ST7FLITE49K2B6
Description
IC MCU 8BIT 8K FLASH 32DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ST7LITE49K2
Figure 51. Dynamic DCR2/3 update in one pulse mode
Force update
In order not to wait for the counter
programmable counter
which when set, make the counters start with the overflow value, i.e. FFFh. After overflow,
the counters start counting from their respective auto reload register values.
These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software
and reset by hardware after the respective counter overflow event has occurred.
This feature can be used at any time. All related features such as PWM generation, Output
Compare, Input Capture, One-pulse (refer to
pulse
Figure 52. Force overflow timing diagram
FORCE2 FORCE1
mode) etc. can be used this way.
f
counter2
FORCE2
PWM2/3
DCR2/3
TRAN2
CNTR2
LTIC
FORCEx
CNTRx
f
CNTRx
ATCSR2 register
(DCR2/3)
E03
x
000
old
overflow is provided. For both counters, a separate bit is provided
E04
FFF
000
FFF
x
overflow to load the value into active DCRx registers, a
(DCR3)
old
ARRx
extra PWM3 period due to DCR3
update dynamically in one-pulse
mode.
Figure 51: Dynamic DCR2/3 update in one
(DCR2/3)
(DCR3)
new
new
ATR2
On-chip peripherals
000
97/245
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