ST72F63BK2M1 STMicroelectronics, ST72F63BK2M1 Datasheet - Page 88

• Manufacturer Part Number: ST72F63BK2M1
• Description: IC MCU 8BIT 8K FLASH 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK2M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
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clock occurs just before the pin value changes, the samples would then be out of sync by
~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample + 4
µs for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
●
●
●
All the deviations of the system should be added and compared to the SCI clock tolerance:
D
Noise error causes
See also description of Noise error in
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
2.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
●
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.
TRA
D
transmitter is transmitting at a different baud rate).
D
D
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
D
A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a “1”.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a “1”.
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
+ D
TRA
QUANT
REC
TCL
QUANT
: Deviation due to the transmission line (generally due to the transceivers)
: Deviation due to transmitter error (Local oscillator error of the transmitter or the
: Deviation of the local oscillator of the receiver: This deviation can occur during
: Error due to the baud rate quantisation of the receiver.
+ D
REC
+ D
TCL
Doc ID 7516 Rev 8
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Section
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ST7263Bxx