ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 25
ST7FDALIF2M6TR
Manufacturer Part Number
ST7FDALIF2M6TR
Description
IC MCU 8BIT 8K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7DALI-EVAL.pdf
(171 pages)
Specifications of ST7FDALIF2M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel / 13 bit, 7 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
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ST7DALIF2
Note:
7.4
7.5
Figure 7.
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
Power saving modes
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active-Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the HALT
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
E2LAT bit
E2PGM bit
DEFINITION
ROW
Data EEPROM write operation
Byte 1
Set by USER application
⇓ Row / Byte ⇒ 0 1 2 3
Writing data latches
Byte 2
PHASE 1
...
N
0
1
Read operation impossible
Byte 32
Waiting E2PGM and E2LAT to fall
Programming cycle
PHASE 2
... 30 31
Nx20h...Nx20h+1Fh
Physical address
00h...1Fh
20h...3Fh
Read operation possible
Cleared by hardware
Data EEPROM
25/171
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