ST72F325J6T6 STMicroelectronics, ST72F325J6T6 Datasheet - Page 100
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ST72F325J6T6
Manufacturer Part Number
ST72F325J6T6
Description
MCU 8BIT 32KB FLASH/ROM 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F325K6T6.pdf
(197 pages)
Specifications of ST72F325J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
3
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Operating Supply Voltage
3.8 V 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5603
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F325J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72325xx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to
mode SCK
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
100/197
SPIE SPE
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
7
Section
Section
Frequency.
SPR2
10.5.5.1
10.5.5.1
MSTR
CPOL
Master
Master
Table 20 SPI Master
CPHA
Mode
Mode
SPR1
SPR0
Fault
Fault
0
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
1: The second clock transition is the first capture
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 20. SPI Master mode SCK Frequency
edge.
edge.
Serial Clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
CPU
CPU
/128
/16
/32
/64
/4
/8
SPR2
1
0
0
1
0
0
SPR1
0
0
0
1
1
1
SPR0
0
0
1
0
0
1