ST72F325J6T6 STMicroelectronics, ST72F325J6T6 Datasheet - Page 162
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ST72F325J6T6
Manufacturer Part Number
ST72F325J6T6
Description
MCU 8BIT 32KB FLASH/ROM 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F325K6T6.pdf
(197 pages)
Specifications of ST72F325J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
3
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Operating Supply Voltage
3.8 V 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5603
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F325J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72325xx
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
(I/O ports and control pins) must not exceed I
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
162/197
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
V
R
V
V
V
I
hys
IO
OL
ON
IH
IL
IO
current sunk must always respect the absolute maximum rating specified in
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Input current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
Parameter
1)
5)
1)
3)
h(RSTL)in
4)
VSS
2)
can be ignored.
.
DD
V
Stretch applied on
external pulse
Internal reset sources
, f
DD
CPU
=5V
Conditions
, and T
I
IO
=+2mA
A
unless otherwise specified.
0.7xV
Min
2.5
20
20
0
DD
Section 12.2.2
Typ
2.5
0.2
200
30
30
2
0.3xV
and the sum of I
Max
120
42
42
0.5
6)
6)
DD
Unit
mA
kΩ
μs
μs
μs
ns
V
V
IO