ST62T25CM6 STMicroelectronics, ST62T25CM6 Datasheet - Page 56

IC MCU 8BIT OTP 4K 28 SOIC

ST62T25CM6

Manufacturer Part Number
ST62T25CM6
Description
IC MCU 8BIT OTP 4K 28 SOIC
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T25CM6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
20
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 16x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
20
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, ST622XC-KIT/110, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
497-2101-5

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Manufacturer
Quantity
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Part Number:
ST62T25CM6
Manufacturer:
ST
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ST6215CM-Auto ST6225CM-Auto
A/D CONVERTER (Cont’d)
9.3.5 Low Power Modes
Note: The A/D converter may be disabled by clear-
ing the PDS bit. This feature allows reduced power
consumption when no conversion is needed.
9.3.6 Interrupts
Note: The EOC bit is cleared only when a new
conversion is started (it cannot be cleared by writ-
ing 0). To avoid generating further EOC interrupt,
the EAI bit has to be cleared within the ADC inter-
rupt subroutine.
9.3.7 Register Description
A/D CONVERTER CONTROL REGISTER (AD-
CR)
Address: 0D1h - Read/Write (Bit 6 Read Only, Bit
5 Write Only)
Reset value: 0100 0000 (40h)
Bit 7 = EAI Enable A/D Interrupt.
0: ADC interrupt disabled
1: ADC interrupt enabled
Bit 6 = EOC End of conversion. Read Only
When a conversion has been completed, this bit is
set by hardware and an interrupt request is gener-
ated if the EAI bit is set. The EOC bit is automati-
Table 15. ADC Register Map and Reset Values
56/100
1
WAIT
STOP
Interrupt Event
End of Conver-
sion
EAI
Address
Mode
7
(Hex.)
0D0h
0D1h
EOC
No effect on A/D Converter. ADC interrupts
cause the device to exit from Wait mode.
A/D Converter disabled.
ADR
Reset Value
ADCR
Reset Value
STA
Register
Label
Event
EOC
Flag
PDS
Description
Enable
ADCR
EAI
ADR7
Bit
3
EAI
7
0
0
OSC
OFF
from
Wait
Exit
Yes
ADR6
EOC
ADCR
6
0
1
1
from
Stop
Exit
No
ADCR
0
0
ADR5
STA
5
0
0
cally cleared when the STA bit is set. Data in the
data conversion register are valid only when this
bit is set to “1”.
0: Conversion is not complete
1: Conversion can be read from the ADR register
Bit 5 = STA: Start of Conversion. Write Only.
0: No effect
1: Start conversion
Note: Setting this bit automatically clears the EOC
bit. If the bit is set again when a conversion is in
progress, the present conversion is stopped and a
new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Bit 4 = PDS Power Down Selection.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 3 = ADCR3 Reserved, must be cleared.
Bit 2 = OSCOFF Main Oscillator off.
0: Main Oscillator enabled
1: Main Oscillator disabled
Note: This bit does not apply to the ADC peripher-
al but to the main clock system. Refer to the Clock
System section.
Bits 1:0 = ADCR[1:0] Reserved, must be cleared.
A/D CONVERTER DATA REGISTER (ADR)
Address: 0D0h - Read only
Reset value: xxxx xxxx (xxh)
Bits 7:0 = ADR[7:0]: 8 Bit A/D Conversion Result.
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
ADR4
7
PDS
4
0
0
ADCR3
ADR3
3
0
0
OSCOFF
ADR2
2
0
0
ADCR1
ADR1
1
0
0
ADCR0
ADR0
0
0
0
0

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