ST72F361J7T3 STMicroelectronics, ST72F361J7T3 Datasheet - Page 94

• Manufacturer Part Number: ST72F361J7T3
• Description: IC MCU 8BIT 48K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J7T3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72361
8-BIT TIMER (Cont’d)
10.5.3.2 Input Capture
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 8-bit
timer.
The two 8-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter (see
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
94/225
Clock Control
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
input capture coming from either the ICAP1 pin
or the ICAP2 pin
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
Table 19 Clock Control
Figure
Bits).
63).
Bits).
Table 19
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiR register.
Notes:
1. The ICiR register contains the free running
counter value which corresponds to the most re-
cent input capture.
2. The two input capture functions can be used to-
gether even if the timer also uses the two output
compare functions.
3. Once the ICIE bit is set both input capture fea-
tures may trigger interrupt requests. If only one is
needed in the application, the interrupt routine
software needs to discard the unwanted capture
interrupt. This can be done by checking the ICF1
and ICF2 flags and resetting them both.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 and ICAP2) are al-
ways directly connected to the timer. So any tran-
sitions on these pins activates the input capture
function.
Moreover if one of the ICAPi pins is configured as
an input and the second one as an output, an inter-
rupt can be generated if the user toggles the output
pin and if the ICIE bit is set.
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond the
timer range (FFh).
running counter on the active transition on the
ICAPi pin (see
and the interrrupt mask is cleared in the CC reg-
ister. Otherwise, the interrupt remains pending
until both conditions become true.
Figure
64).