ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 104

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
8-BIT TIMER (Cont’d)
10.5.4 Low Power Modes
10.5.5 Interrupts
Note: The 8-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
10.5.6 Summary of Timer modes
1) See note 4 in
2) See note 5 in
3) See note 4 in
104/265
WAIT
HALT
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
Mode
MODES
No effect on 8-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
8-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
“One Pulse Mode” on page 100
“One Pulse Mode” on page 100
“Pulse Width Modulation Mode” on page 102
Interrupt Event
Input Capture 1
Yes
No
Not Recommended
Not Recommended
Input Capture 2
Description
AVAILABLE RESOURCES
Yes
1)
3)
Output Compare 1 Output Compare 2
Event
OCF1
OCF2
ICF1
ICF2
Flag
TOF
Yes
No
Control
Enable
OCIE
TOIE
ICIE
Bit
from
Wait
Exit
Yes
Partially
Yes
No
from
Halt
Exit
2)
No