ST72F321AR9TA STMicroelectronics, ST72F321AR9TA Datasheet - Page 39

• Manufacturer Part Number: ST72F321AR9TA
• Description: IC MCU 8BIT 60KB FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321AR9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
- ei3 (port B7..4)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
IS11 IS10
IS11 IS10
IS11
0
0
1
1
0
0
1
1
7
IS10
0
1
0
1
0
1
0
1
Falling edge only
Rising edge only
IPB
Falling edge &
IPB bit =0
low level
External Interrupt Sensitivity
External Interrupt Sensitivity
IS21
Falling edge & low level
Rising and falling edge
Rising and falling edge
Falling edge only
Rising edge only
IS20
IPA
Falling edge only
Rising edge only
Rising edge
& high level
IPB bit =1
TLIS TLIE
0
- ei0 (port A3..0)
- ei1 (port F2..0)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 1 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
IS21 IS20
IS21 IS20
0
0
1
1
0
0
1
1
ST72321Rx ST72321ARx ST72321Jx
0
1
0
1
0
1
0
1
Falling edge only
Rising edge only
Falling edge &
IPA bit =0
low level
External Interrupt Sensitivity
External Interrupt Sensitivity
Falling edge & low level
Rising and falling edge
Rising and falling edge
Falling edge only
Rising edge only
Falling edge only
Rising edge only
Rising edge
& high level
IPA bit =1
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