Z86E7216PSG Zilog, Z86E7216PSG Datasheet - Page 39

• Manufacturer Part Number: Z86E7216PSG
• Description: IC 16K OTP ZIRC 40-DIP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E7216PSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 748 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS008704-0507
/RESET (Input, Active Low)
Note:
Reset initializes the MCU. Reset is accomplished either through Power-On,
Watch-Dog Timer, Stop-Mode Recovery, Low-Voltage detection, or external reset.
During Power-On Reset and Watch-Dog Timer Reset, the internally generated
reset drives the reset pin Low for the POR time. Any devices driving the reset line
need to be open-drain to avoid damage from a possible conflict during reset con-
ditions. Pull-up is provided internally. There is no condition internal to the Z86E7X
that does not allow an external reset to occur.
After the POR time, /RESET is a Schmitt-triggered input. To avoid asynchronous
and noisy reset problems, the Z86E7X is equipped with a reset filter of four exter-
nal clocks (4TpC). If the external reset signal is less than 4TpC in duration, no
reset occurs. On the fifth clock after the reset is detected, an internal RST signal is
latched and held for an internal register count of 18 external clocks or for the dura-
tion of the external reset, whichever is longer.
During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2.
Program execution begins at location 000CH, 5–10 TpC cycles after the RST is
released. For Power-On Reset, the typical reset output time is 5 ms.
The Z86E7X devices do not have internal pull resistors on
Port 3 inputs.
OTP Microcontroller
35