Z86E7216PSG Zilog, Z86E7216PSG Datasheet - Page 73
![IC 16K OTP ZIRC 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z86E7216PSG
Manufacturer Part Number
Z86E7216PSG
Description
IC 16K OTP ZIRC 40-DIP
Manufacturer
Zilog
Series
Z8®r
Datasheet
1.Z86E7216PSC.pdf
(102 pages)
Specifications of Z86E7216PSG
Core Processor
Z8
Core Size
8-Bit
Speed
16MHz
Peripherals
LVD, POR, WDT
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
748 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.620", 15.75mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
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- Download datasheet (2Mb)
PS008704-0507
Note:
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a Divide-by-16 prescaler of SCLK/TCLK
purpose of this control is to selectively reduce device power consumption during
normal processor execution (SCLK control) and/or HALT Mode (where TCLK
sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0.
Stop-Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the STOP recovery
(Figure 40
Table 28. Stop-Mode Recovery Source
Divide
Divide
by 16
OSC
D4
by 2
0
0
0
0
1
1
1
1
SMR:432
Any Port 2 bit defined as an output drives the corresponding
input to the default state to allow the remaining inputs to control
the AND/OR function. Refer to “Stop-Mode Recovery Register
2 (SMR2)” on page 71 for other recovery sources.
SMR, D0
D3
0
0
1
1
0
0
1
1
on page 68 and
D2
0
1
0
1
0
1
0
1
SCLK
TCLK
Figure 41. SCLK Circuit
POR and/or external reset recovery
Reserved
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Table
Description of Action
28).
Operation
OTP Microcontroller
(Figure
41). The
69
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