STM32F103ZDH6 STMicroelectronics, STM32F103ZDH6 Datasheet - Page 104

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STM32F103ZDH6

Manufacturer Part Number
STM32F103ZDH6
Description
MCU ARM 32BIT 384KB FLASH 144BGA
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103ZDH6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 21x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-BGA
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
112
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
3 (12 bit, 16 Channel)
On-chip Dac
2 (12 bit, 2 Channel)
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Eeprom Size
-
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Electrical characteristics
Table 62.
1. Guaranteed by design, not tested in production.
2. Guaranteed by characterization, not tested in production.
Figure 57. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
104/123
Offset
Gain
error
t
Update
rate
t
PSRR+
SETTLING
WAKEUP
Symbol
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
(2)
(2)
(2)
(1)
(2)
(2)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
Power supply rejection ratio
(to V
measurement
DAC characteristics (continued)
REF+
DDA
/2)
) (static DC
Parameter
Buffered/Non-buffered DAC
12-bit
digital to
analog
converter
Min
Doc ID 14611 Rev 7
3
6.5
–67
Buffer(1)
Typ
±10
±3
±12
±0.5
4
1
10
–40
STM32F103xC, STM32F103xD, STM32F103xE
Max
DACx_OUT
mV
LSB
LSB
%
µs
MS/s C
µs
dB
Unit
C
R
Given for the DAC in 12-bit
configuration
Given for the DAC in 10-bit at V
= 3.6 V
Given for the DAC in 12-bit at V
= 3.6 V
Given for the DAC in 12bit
configuration
C
C
input code between lowest and
highest possible ones.
No R
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
 50 pF, R
 50 pF, R
 50 pF, R
, C
LOAD
Comments
ai17157
LOAD
LOAD
LOAD
= 50 pF
 5 k
 5 k
 5 k
REF+
REF+

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