STM32F103ZDH6 STMicroelectronics, STM32F103ZDH6 Datasheet - Page 82

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STM32F103ZDH6

Manufacturer Part Number
STM32F103ZDH6
Description
MCU ARM 32BIT 384KB FLASH 144BGA
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103ZDH6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 21x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-BGA
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
112
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
3 (12 bit, 16 Channel)
On-chip Dac
2 (12 bit, 2 Channel)
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Eeprom Size
-
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Electrical characteristics
5.3.13
Table 45.
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
82/123
Symbol
V
R
R
C
V
V
V
V
I
MOS/NMOS contribution
lkg
hys
PU
PD
IH
IH
IO
IL
IL
Input low level voltage
Standard IO input high level voltage
IO FT
Input low level voltage
Input high level voltage
Standard IO Schmitt trigger voltage
hysteresis
IO FT Schmitt trigger voltage
hysteresis
Input leakage current
Weak pull-up equivalent resistor
Weak pull-down equivalent resistor
I/O pin capacitance
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44.
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
Symbol
(1)
LU
input high level voltage
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
(2)
(2)
Parameter
to the series resistance is minimum
Static latch-up class
Electrical sensitivities
(4)
Parameter
(5)
(5)
Doc ID 14611 Rev 7
V
V
T
Standard I/Os
CMOS ports
SS
A
IN
Conditions
(~10% order)
TTL ports
V
V
+105 °C conforming to JESD78A
= 5 V,
IN
IN
V


IN
V
V
I/O FT
DD
STM32F103xC, STM32F103xD, STM32F103xE
SS
V
DD
.
Table
Conditions
5% V
Table 45
0.65 V
10. All I/Os are CMOS and TTL
–0.5
–0.5
Min
200
30
30
2
2
DD
DD
(3)
are derived from tests
Typ
40
40
5
0.35 V
V
V
DD
DD
5.5V
Max
0.8
1
50
50
3
+0.5
+0.5
DD
II level A
Class
Unit
mV
mV
µA
k
k
pF
V
V

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