C8051F305-GMR Silicon Laboratories Inc, C8051F305-GMR Datasheet - Page 131

• Manufacturer Part Number: C8051F305-GMR
• Description: IC 8051 MCU 2K FLASH 11QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• For Use With: 336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

14. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Reading SBUF0
accesses the buffered Receive register; writing SBUF0 accesses the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Section “14.1. Enhanced Baud Rate Generation” on page
Rate Generator
UART Baud
Write to
SBUF
Figure 14.1. UART0 Block Diagram
Rx Clock
Tx Clock
Stop Bit
Start
Start
SBUF
Read
SCON0
D
TB8
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
Rx Control
(9 bits)
Tx Control
SBUF
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF
RB8
Load SBUF0
Rev. 2.9
Tx IRQ
Rx IRQ
TI
RI
SBUF
Load
Send
Data
C8051F300/1/2/3/4/5
Interrupt
Serial
Port
132). Received data buffering allows
TX
RX
Crossbar
Crossbar
Port I/O
131