C8051F305-GMR Silicon Laboratories Inc, C8051F305-GMR Datasheet - Page 149

• Manufacturer Part Number: C8051F305-GMR
• Description: IC 8051 MCU 2K FLASH 11QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• For Use With: 336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits
R/W
Bit7
—
UNUSED. Read = 0b, Write = don’t care.
T2MH: Timer 2 High Byte Clock Select
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-
bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML: Timer 2 Low Byte Clock Select
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
UNUSED. Read = 0b, Write = don’t care.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
Note: External clock divided by 8 is synchronized with the
SCA1
T2MH
0
0
1
1
R/W
Bit6
system clock, and the external clock must be less
than or equal to the system clock to operate in this
mode.
SCA0
SFR Definition 15.3.
0
1
0
1
T2ML
R/W
Bit5
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8
T1M
R/W
Bit4
Prescaled Clock
Rev. 2.9
T0M
R/W
Bit3
CKCON: Clock Control
R/W
Bit2
—
C8051F300/1/2/3/4/5
SCA1
R/W
Bit1
SCA0
R/W
Bit0
SFR Address:
00000000
Reset Value
0x8E
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