HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 35

• Manufacturer Part Number: HD64F3672FPV
• Description: IC H8/3672 MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 1.3
Type
Data transfer
Arithmetic
operations
Instructions Classified by Function
Instruction
MOV
MOVFPE
MOVTPE
POP
PUSH
ADD
SUB
ADDX
SUBX
INC
DEC
Size *
B/W/L
B
B
W/L
W/L
B/W/L
B
B/W/L
Function
(EAs)
Moves data between two general registers or between
a general register and memory, or moves immediate
data to a general register.
(EAs)
Moves external memory contents (addressed by
@aa:16) to a general register in synchronization with
an E clock.
Rs
Moves general register contents to an external memory
location (addressed by @aa:16) in synchronization with
an E clock.
@SP+
Pops a register from the stack. POP.W Rn is identical
to MOV.W @SP+, Rn. POP.L ERn is identical to
MOV.L @SP+, ERn.
Rn
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is
identical to MOV.L ERn, @–SP.
Rd ± Rs
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from data in a general register. Use the SUBX or ADD
instruction.)
Rd ± Rs ± C
Performs addition or subtraction with carry or borrow
on byte data in two general registers, or on immediate
data and data in a general register.
Rd ± 1
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
(EAd)
@–SP
Rd, Rs
Rd
Rn
Rd, Rd ± 2
Rd, Rd ± #IMM
Rev. 3.00 Dec 13, 2004 page 19 of 258
Rd, Rd ± #IMM ± C
(EAd)
Rd
Rd
REJ09B0213-0300
Rd
Section 1 CPU