HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 69

• Manufacturer Part Number: HD64F3672FPV
• Description: IC H8/3672 MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bcc
Notes
1. The branch destination address must be even.
2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO,
Bcc (Branch conditionally)
Operand Format and Number of States Required for Execution
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Program-counter
relative
Addressing
respectively. The number of execution states for BRn (BF) is the same as for two NOP
instructions.
Mode
BRA (BT)
BRN (BF)
BHI
BLS
Bcc (BHS)
BCS (BLO)
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
Mnemonic
Operands
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
d:8
d:16
1st byte
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
C
D
A
B
E
F
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
8
8
8
8
8
8
8
2nd byte
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
Instruction Format
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
Rev. 3.00 Dec 13, 2004 page 53 of 258
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2 Instruction Descriptions
3rd byte
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
Conditional Branch
4th byte
REJ09B0213-0300
States
No. of
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6