MC9S08GT60ACFDE Freescale Semiconductor, MC9S08GT60ACFDE Datasheet - Page 90

• Manufacturer Part Number: MC9S08GT60ACFDE
• Description: IC MCU 60K FLASH 4K RAM 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60ACFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output
90
PTASE[7:0]
PTADD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTADD7
PTASE7
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
0
0
7
7
PTADD6
PTASE6
Figure 6-11. Slew Rate Control Enable for Port A (PTASE)
0
0
6
6
Figure 6-12. Data Direction for Port A (PTADD)
Table 6-4. PTADD Field Descriptions
Table 6-3. PTASE Field Descriptions
PTADD5
PTASE5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTADD4
PTASE4
0
0
4
4
Description
Description
PTADD3
PTASE3
3
0
3
0
PTADD2
PTASE2
0
0
2
2
PTADD1
PTASE1
Freescale Semiconductor
0
0
1
1
PTADD0
PTASE0
0
0
0
0