MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 162

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3
This section provides a detailed description of all registers accessible in the ATD.
5.3.1
Figure 5-2
5.3.2
This section describes in address order all the ATD registers and their individual bits.
162
Unimplemente
ATDTEST0
ATDTEST1
ATDSTAT0
ATDCTL0
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
Register
Name
d
Memory Map and Register Definition
gives an overview of all ATD registers.
Module Memory Map
Register Descriptions
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
ETRIGSEL
SRES8
ADPU
Bit 7
DJM
SCF
U
U
0
0
Figure 5-2. ATD Register Summary (Sheet 1 of 5)
= Unimplemented or Reserved
DSGN
SMP1
AFFC
MC9S12XDP512 Data Sheet, Rev. 2.21
S8C
U
U
6
0
0
0
ETORF
SMP0
SCAN
AWAI
S4C
U
5
0
0
0
NOTE
ETRIGLE
FIFOR
PRS4
MULT
S2C
U
4
0
0
0
ETRIGP
PRS3
S1C
U
3
0
0
0
0
0
ETRIGCH2 ETRIGCH1 ETRIGCH0
ETRIGE
WRAP2
PRS2
FIFO
CC2
CC
U
2
0
Freescale Semiconductor
WRAP1
ASCIE
PRS1
FRZ1
CC1
CB
U
1
0
WRAP0
ASCIF
PRS0
FRZ0
Bit 0
CC0
CA
SC
U