MCF52274CLU120 Freescale Semiconductor, MCF52274CLU120 Datasheet - Page 26
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MCF52274CLU120
Manufacturer Part Number
MCF52274CLU120
Description
MCU 32-BIT LCD TOUCH 176-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5227xr
Datasheet
1.MCF52277CVM160J.pdf
(46 pages)
Specifications of MCF52274CLU120
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, LCD, PWM, WDT
Number Of I /o
47
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LQFP
Family Name
MCF5227x
Device Core
ColdFire
Device Core Size
16b
Frequency (max)
120MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5/1.8/2.5/3.3V
Operating Supply Voltage (max)
1.6/3.6V
Operating Supply Voltage (min)
1.4/1.7/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52274CLU120
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Electrical Characteristics
26
DD10 Input Data Hold Relative to DQS
DD11 DQS falling edge from SDCLK rising (output hold time) t
Num
DD8
DD9
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
SD_CLK is one SDRAM clock in ns.
Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
Data and Data Mask Output Hold (DQS→DQ) Relative
to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
Characteristic
MCF5227x ColdFire
Table 15. DDR Timing Specifications (continued)
®
Microprocessor Data Sheet, Rev. 8
Symbol
DQLSDCH
t
t
DQDMI
t
DVDQ
DIDQ
0.25 × SD_CLK
+ 0.5ns
Min
1.0
0.5
—
Max
—
—
—
1
Freescale Semiconductor
Unit
ns
ns
ns
ns
Notes
7
8
9