MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 1042
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
25.3.2.1
The ECLKDIV register is used to control timed events in program and erase algorithms.
All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
25.3.2.2
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
25.3.2.3
This register is reserved for factory testing and is not accessible.
1044
EDIV[5:0]
EDIVLD
PRDIV8
Reset
Reset
Field
5:0
7
6
W
W
R
R
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input
oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
Section 25.4.1.1, “Writing the ECLKDIV Register”
Enable Prescalar by 8
EEPROM Clock Divider Register (ECLKDIV)
RESERVED1
RESERVED2
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PRDIV8
Figure 25-4. EEPROM Clock Divider Register (ECLKDIV)
0
0
0
6
6
Table 25-2. ECLKDIV Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
EDIV5
0
0
0
5
5
Figure 25-5. RESERVED1
EDIV4
0
0
0
4
4
Description
for more information.
EDIV3
0
0
0
3
3
EDIV2
0
0
0
2
2
Freescale Semiconductor
EDIV1
0
0
0
1
1
EDIV0
0
0
0
0
0
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