MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 930
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.19 Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.
In this case the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
23.0.5.20 Port T Reduced Drive Register (RDRT)
Read: Anytime.
Write: Anytime.
932
DDRT[7:0]
PTIT[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRT7
RDRT7
Port T Input — This register always reads back the buffered state of the associated pins. This can also be used
to detect overload or short circuit conditions on output pins.
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
0
7
7
on PTT or PTIT registers, when changing the DDRT register.
DDRT6
RDRT6
0
0
6
6
Figure 23-22. Port T Reduced Drive Register (RDRT)
Figure 23-21. Port T Data Direction Register (DDRT)
Table 23-23. DDRT Field Descriptions
Table 23-22. PTIT Field Descriptions
DDRT5
RDRT5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDRT4
RDRT4
0
0
4
4
Description
Description
DDRT3
RDRT3
0
0
3
3
DDRT2
RDRT2
0
0
2
2
DDRT1
RDRT1
Freescale Semiconductor
0
0
1
1
DDRT0
RDRT0
0
0
0
0
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