MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 725
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC9S12XA512CAG
Manufacturer:
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Quantity:
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Part Number:
MC9S12XA512CAG
Manufacturer:
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19.4.5.3.2
The data stored in the trace buffer can be read using either the background debug module (BDM) module
or the CPU provided the DBG module is not armed, is configured for tracing (at least one TSOURCE bit
is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when
the module is disarmed. Multiple writes to the DBGTB are not allowed since they increment the pointer.
The trace buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1
and 0 of
Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the
RAM pointer will occur. Reading the trace buffer is not possible if both TSOURCE bits are cleared.
Freescale Semiconductor
XOCF
Field
XRW
1
0
Table
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing XGATE activity in detail mode.
0 Read/Write Access
1 Access
XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle.This bit only contains valid information when tracing the CPU accesses in detail mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
19-39. The bytes containing invalid information (shaded in
Reading Data from Trace Buffer
Table 19-42. CXINF Field Descriptions (continued)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Chapter 19 S12X Debug (S12XDBGV2) Module
Table
19-39) are also read out.
727
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