MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 148
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.12
Read: Anytime
Write: anytime
4.3.2.13
Read: Anytime
Write: Anytime
148
IEN[15:8]
Reset
Reset
IEN[7:0]
Field
Field
7:0
7:0
W
W
R
R
IEN15
IEN7
ATD Input Enable Register 0 (ATDDIEN0)
ATD Input Enable Register 1 (ATDDIEN1)
0
0
7
7
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
IEN14
IEN6
0
0
6
6
Figure 4-14. ATD Input Enable Register 0 (ATDDIEN0)
Figure 4-15. ATD Input Enable Register 1 (ATDDIEN1)
Table 4-23. ATDDIEN0 Field Descriptions
Table 4-24. ATDDIEN1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
IEN13
IEN5
0
0
5
5
IEN12
IEN4
0
0
4
4
Description
Description
IEN11
IEN3
0
0
3
3
IEN10
IEN2
0
0
2
2
Freescale Semiconductor
IEN9
IEN1
0
0
1
1
IEN8
IEN0
0
0
0
0
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