MC68HC711D3CFNE3 Freescale Semiconductor, MC68HC711D3CFNE3 Datasheet - Page 61

• Manufacturer Part Number: MC68HC711D3CFNE3
• Description: IC MCU 8BIT 2MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5.5.2 STOP
TECHNICAL DATA
nals driving on-chip peripheral functions can be shut down. The CPU is always shut
down during WAIT. While in the wait state, the address/data bus repeatedly runs read
cycles to the address where the CCR contents were stacked. The MPU leaves the wait
state when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if the I bit is set to one and the COP
system is disabled by NOCOP being set to one. Several other systems can also be in
a reduced power consumption state depending on the state of software-controlled
configuration control bits. The SPI system is enabled or disabled by the SPE control
bit. The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is
enabled or disabled by the RE bit. Therefore the power consumption in WAIT is de-
pendent on the particular application.
Executing the STOP instruction while the S bit in the CCR is equal to zero places the
MCU in the STOP condition. If the S bit is not zero, the STOP opcode is treated as a
no-op (NOP). The STOP condition offers minimum power consumption because all
clocks, including the crystal oscillator, are stopped while in this mode. To exit STOP
and resume normal processing, a logic low level must be applied to one of the external
interrupts (IRQ or XIRQ), or to the RESET pin. A pending edge-triggered IRQ can also
bring the CPU out of STOP.
Because all clocks are stopped in this mode, all internal peripheral functions also stop.
The data in the internal RAM is retained as long as V
state and I/O pin levels are static and are unchanged by STOP. Therefore, when an
interrupt comes to restart the system, the MCU resumes processing as if there were
no interruption. If reset is used to restart the system a normal reset sequence results
where all I/O pins and functions are also restored to their initial states.
To use the IRQ pin as a means of recovering from STOP, the I bit in the CCR must be
clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from STOP
regardless of the state of the X bit in the CCR, although the recovery sequence de-
pends on the state of the X bit. If X is set to zero (XIRQ not masked), the MCU starts
up, beginning with the stacking sequence leading to normal service of the XIRQ re-
quest. If X is set to one (XIRQ masked or inhibited), then processing continues with
the instruction that immediately follows the STOP instruction, and no XIRQ interrupt
service is requested or pending.
Because the oscillator is stopped in STOP mode, a restart delay may be imposed to
allow oscillator stabilization upon leaving STOP. If the internal oscillator is being used,
this delay is required; however, if a stable external oscillator is being used, the DLY
control bit can be used to bypass this startup delay. The DLY control bit is set by reset
and can be optionally cleared during initialization. If the DLY equal to zero option is
used to avoid startup delay on recovery from STOP, then reset should not be used as
the means of recovering from STOP, as this causes DLY to be set again by reset, im-
posing the restart delay. This same delay also applies to power-on-reset, regardless
of the state of the DLY control bit, but does not apply to a reset while the clocks are
running.
Freescale Semiconductor, Inc.
For More Information On This Product,
RESETS AND INTERRUPTS
Go to: www.freescale.com
DD
power is maintained. The CPU
5-17