C8051F006-GQR Silicon Laboratories Inc, C8051F006-GQR Datasheet - Page 115
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C8051F006-GQR
Manufacturer Part Number
C8051F006-GQR
Description
IC 8051 MCU 32K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F00xr
Specifications of C8051F006-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
For Use With
336-1188 - DEV KIT FOR F005/006/007
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F006-GQR
Manufacturer:
SILICON
Quantity:
1 200
Company:
Part Number:
C8051F006-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
16.2.
A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of
data, and a STOP condition. The address byte and each of the data bytes are followed by an ACKNOWLEDGE bit
from the receiver. The address byte consists of a 7-bit address plus a direction bit. The direction bit (R/W)
occupies the least-significant bit position of the address. The direction bit is set to logic 1 to indicate a “READ”
operation and cleared to logic 0 to indicate a “WRITE” operation. A general call address (0x00 +R/W) is
recognized by all slave devices allowing a master to address multiple slave devices simultaneously.
All transactions are initiated by the master, with one or more addressed slave devices as the target.
generates the START condition and then transmits the address and direction bit. If the transaction is a WRITE
operation from the master to the slave, the master transmits the data a byte at a time waiting for an
ACKNOWLEDGE from the slave at the end of each byte. If it is a READ operation, the slave transmits the data
waiting for an ACKNOWLEDGE from the master at the end of each byte. At the end of the data transfer, the
master generates a STOP condition to terminate the transaction and free the bus. Figure 16.3 illustrates a typical
SMBus transaction.
The SMBus interface may be configured to operate as either a master or a slave. At any particular time, it will be
operating in one of the following four modes:
16.2.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The first byte transmitted contains the
address of the target slave device and the data direction bit. In this case the data direction bit (R/W) will be logic 0
to indicate a “WRITE” operation. The master then transmits one or more bytes of serial data. After each byte is
transmitted, an acknowledge bit is generated by the slave. To indicate the beginning and the end of the serial
transfer, the master device outputs START and STOP conditions.
16.2.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The first byte is transmitted by the master
and contains the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will
be logic 1 to indicate a “READ” operation. Serial data is then received from the slave on SDA while the master
outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, an
acknowledge bit is transmitted by the master. The master outputs START and STOP conditions to indicate the
beginning and end of the serial transfer.
16.2.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 1 to indicate a “READ”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are transmitted to the master. After each byte is received, an acknowledge bit is
transmitted by the master. The master outputs START and STOP conditions to indicate the beginning and end of
the serial transfer.
115
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
START
Operation
SLAVE ADDR R/W
Figure 16.3. SMBus Transaction
ACK
DATA
Rev. 1.7
Time
ACK
DATA
NACK
STOP
The master