C8051F006-GQR Silicon Laboratories Inc, C8051F006-GQR Datasheet - Page 96
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C8051F006-GQR
Manufacturer Part Number
C8051F006-GQR
Description
IC 8051 MCU 32K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F00xr
Specifications of C8051F006-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
For Use With
336-1188 - DEV KIT FOR F005/006/007
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F006-GQR
Manufacturer:
SILICON
Quantity:
1 200
Company:
Part Number:
C8051F006-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
13.8.1. Watchdog Usage
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period
between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is
generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired.
Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 13.3.
Enable/Reset WDT
The watchdog timer is both enabled and the countdown restarted by writing 0xA5 to the WDTCN register. The
user’s application software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog
timer overflow. The WDT is enabled and restarted as a result of any system reset.
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT.
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored.
Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the
next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use
the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
For a 2MHz system clock, this provides an interval range of 0.032msec to 524msec. WDTCN.7 must be a 0 when
setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is 111b after a system
reset.
Bits7-0: WDT Control
Bit4:
Bits2-0: Watchdog Timeout Interval Bits
R/W
Bit7
CLR
MOV
MOV
SETB
4
3+WDTCN[2:0]
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
EA
WDTCN,#0DEh ; disable software
WDTCN,#0ADh ; watchdog timer
EA
R/W
Bit6
Figure 13.3. WDTCN: Watchdog Timer Control Register
x T
SYSCLK
R/W
, (where T
Bit5
; disable all interrupts
; re-enable interrupts
SYSCLK
R/W
Bit4
is the system clock period).
Rev. 1.7
R/W
Bit3
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
xxxxx111
0xFF
96