M30281F6HP#U5B Renesas Electronics America, M30281F6HP#U5B Datasheet - Page 200

• Manufacturer Part Number: M30281F6HP#U5B
• Description: IC M16C/28 MCU FLASH 48K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F6HP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
1
Figure 14.10 Typical transmit/receive timings in clock synchronous serial I/O mode
. v
J
6
0
C
2
9
2 /
The above timing diagram applies to the case where the register bits are set as follows:
0 .
B
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
CTSi
CLKi
TxDi
UiC0 register
TXEPT bit
SiTIC register
IR bit
The above timing diagram applies to the case where the register bits are set
as follows:
f
(2) Example of Receive Timing (External clock is selected)
• The CKDIR bit in the UiMR register is set to "0" (internal clock)
• The CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled); CRS bit is set to "0" (CTS selected)
• The CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the
• The UiIRS bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the bit 0 in the UCON register
(1) Example of Transmit Timing (Internal clock is selected)
EXT
0
8
0
transfer clock)
U1IRS bit is the bit 1 in the UCON register, and U2IRS bit is the bit 4 in the U2C1 register.
• The CKDIR bit in the UiMR register is set to "1" (external clock)
• The CRD bit in the UiC0 register is set to "0"(CTS/RTS enabled);
• UiC0 register CKPOL bit is set to "0"(transmit data output at the falling edge and
UiC1 register
RE bit
CLKi
RxDi
UiC1 register
TE bit
UiC1 register
TI bit
RTSi
UiC1 register
RI bit
SiRIC register
IR bit
0
The CRS bit is set to "1" (RTS selected)
receive data taken in at the rising edge of the transfer clock)
G
4
: frequency of external clock
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
“H”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
0
6
“H”
“L”
“1”
“0”
“1”
“0”
7
“1”
“0”
“1”
“0”
“1”
“0”
C
2 /
Transferred from UARTi receive register
page 178
, 8
Write data to the UiTB register
M
D
1
0
D
Transferred from UiTB register to UARTi transmit register
6
Write dummy data to UiTB register
0
D
C
1
D
2 /
f o
T
1
D
CLK
2
8
D
3
2
D
) B
8
3
to UiRB register
Transferred from UiTB register to UARTi transmit register
D
5
3
D
Tc
4
D
4
D
1 / f
Receive data is taken in
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
5
D
5
Cleared to “0” when interrupt request is
accepted, or cleared to “0” by program
D
EXT
6
D
6
D
7
D
Stopped pulsing because CTSi = “H”
7
Read out from UiRB register
D
0
D
D
0
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
Tc = T
1
D
D
1
2
fj: frequency of UiBRG count source (f
n: value set to UiBRG register
D
i: 0 to 2
CLK
D
2
3
D
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
3
D
= 2(n + 1) / fj
• UiC0 register TE bit is set to "1" (transmit enabled)
• UiC0 register RE bit is set to "1" (Receive enabled)
• Write dummy data to the UiTB register
4
D
4
D
5
D
D
5
6
D
7
Stopped pulsing because the TE bit = “0”
D
0
D
1
D
1SIO
2
D
, f
3
2SIO
D
4
, f
D
8SIO
5
D
6
, f
32SIO
D
14.Serial I/O
7
)