M30281F6HP#U5B Renesas Electronics America, M30281F6HP#U5B Datasheet - Page 299

• Manufacturer Part Number: M30281F6HP#U5B
• Description: IC M16C/28 MCU FLASH 48K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F6HP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.13 Address Data Communication
e
E
1
Figure 16.20 Address data communication format
. v
J
6
0
This section describes data transmit control when a master transferes data or a slave receives data in 7-bit
address format. Figure 16.20 (1) shows a master transmit format.
16.13.1 Example of Master Transmit
C
2
9
For example, a master transmits data as shown below when following conditions are met: standard clock
mode, SCL clock frequency of 100kHz and ACK clock added.
0 .
2 /
B
0
0
8
10) Set “C0
11) Write dummy data to the S00 regiser to generate STOP condition
0
1) Set s slave address to the 7 high-order bits in the S0D0 register
2) Set “85
3) Set “00
4) Set “08
5) Confirm whether the bus is free by BB flag setting in the S10 register
6) Set “E0
7) Set the destination address in 7 high-order bits and "0" to a least significant bit in the S00 register
8) Set a transmit data to the S00 register. At this time, SCL and an ACK clock are automatically
9) When transmitting more than 1-byte control data, repeat the above step 8).
4
G
J
7
a
o r
0 -
the slave receiver or if the transmit is completed
. n
S3D0 registe to generate an ACK clock and set SCL clock frequency t 100 kHz (f
to generate START condition. At this time, the first byte consisting of SCL and ACK clock are
automatically generated
generated
u
2
3
p
0
, 1
0
(
M
2
0
16
1
16
16
16
16
0
6
” to the S20 register, “000
7
” to the S10 register to reset transmit/receive
” to the S1D0 register to enable data communication
” to the S10 register to enter START condition standby mode
C
” in the S10 register to enter STOP condition standby mode if ACK is not returned from
2 /
page 277
(1) A master transmit device transmits data to a receive device
(2) A master receive device receives data from a transmit device
, 8
S :
A :
S
S
M
START condition
ACK bit
1
6
C
Slave address
Slave address
f o
2 /
7 bits
7 bits
8
3
) B
8
5
R/W
R/W
“0”
“1”
2
” to the ICK4 to ICK2 bits in the S4D0 register and “00
P
R/W :
A
A
:
STOP condition
Read/Write bit
1 - 8 bits
1 - 8 bits
Data
Data
A
A
1 - 8 bits
1 - 8 bits
Data
Data
16. MULTI-MASTER I
A/A
A
P
P
2
1
C bus INTERFACE
=8MHz, f
16
” to the
IIC
=f1)