M38227ECFP Renesas Electronics America, M38227ECFP Datasheet - Page 28

IC 740 MCU EPROM 48K 80QFP

M38227ECFP

Manufacturer Part Number
M38227ECFP
Description
IC 740 MCU EPROM 48K 80QFP
Manufacturer
Renesas Electronics America
Series
740/38000r
Datasheet

Specifications of M38227ECFP

Core Processor
740
Core Size
8-Bit
Speed
8MHz
Connectivity
SIO, UART/USART
Peripherals
LCD
Number Of I /o
49
Program Memory Size
48KB (48K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number:
M38227ECFP
Manufacturer:
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Quantity:
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Manufacturer:
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Quantity:
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TIMERS
The 3822 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Fig. 21 Timer block diagram
I n t e r n a l c l o c k
P 5
P 5
P5
5
4
/ C N T R
= X
/ C N T R
6
P 5
/T
C I N
P 5
P5
P 5
P 5
OUT
4
P5
/ 2
2
3
2
3
d i r e c t i o n r e g i s t e r
1
d i r e c t i o n r e g i s t e r
direction register
0
6
f(X
(f(X
direction register
IN
CIN
)/16
CNTR
edge switch bit
f ( X
( f ( X
Pulse width
measurement
mode
)/16 in low-speed mode
f ( X
C N T R
e d g e s w i t c h b i t
R e a l t i m e p o r t
c o n t r o l b i t “ 1 ”
R e a l t i m e p o r t
c o n t r o l b i t “ 1 ”
I N
I N
I N
Timer 1 count source
selection bit
) / 1 6
T
control bit
) / 1 6 ( f ( X
) / 1 6 i n l o w - s p e e d m o d e )
X
OUT
1
CIN
0
active
P u l s e o u t p u t m o d e
a c t i v e
“ 0 ”
“ 1 ”
CNTR
edge switch bit
output
P 5
P 5
“0”
“ 1 ”
“ 0 ”
“ 0 ”
C I N
2
3
“ 0 ”
“ 1 ”
l a t c h
l a t c h
) / 1 6 i n l o w - s p e e d m o d e )
f(X
(f(X
0
P 5
P5
Timer X operat-
ing mode bits
“00”,“01”,“11”
“ 1 0 ”
T
a c t i v e e d g e
s w i t c h b i t
“ 0 0 ” , “ 0 1 ” , “ 1 1 ”
active
IN
O U T
CIN
)/16
6
4
L a t c h
L a t c h
“ 1 0 ”
Q D
Q D
l a t c h
)516 in low-speed mode )
latch
Timer Y operating
mode bits
o u t p u t
]
)
T i m e r 1 l a t c h ( 8 )
“ 0 ”
“1”
“0”
“1”
T i m e r 1 ( 8 )
T
c o n t r o l b i t
Real time port
control bit “0”
O U T
Q
Q
Q
Q
S
Timer X stop
control bit
S
P 5
P 5
o u t p u t
T i m e r Y s t o p
c o n t r o l b i t
T
T
2
3
16
T i m e r Y ( l o w ) l a t c h ( 8 )
d a t a f o r r e a l t i m e p o r t
d a t a f o r r e a l t i m e p o r t
”,
Timer Y (low) (8)
R i s i n g e d g e d e t e c t i o n
Falling edge detection
T i m e r 3 c o u n t
s o u r c e s e l e c t i o n b i t
T i m e r X ( l o w ) l a t c h ( 8 )
“1”
Pulse output mode
f ( X
( f ( X
Timer 2 count source
selection bit
Timer X (low) (8)
“ 0 ”
I N
“ 1 ”
C I N
) / 1 6
“ 0 ”
“ 1 ”
Pulse width HL continuously measurement mode
) / 1 6 i n l o w - s p e e d m o d e )
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Timer X mode register
write signal
Timer 3 latch (8)
Timer 3 (8)
T i m e r 2 l a t c h ( 8 )
Timer Y (high) latch (8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 2 (8)
T i m e r Y ( h i g h ) ( 8 )
Timer X (high) latch (8)
Period
measurement mode
Timer X (high) (8)
T i m e r Y o p e r a t i n g m o d e b i t s
MITSUBISHI MICROCOMPUTERS
Timer X write
control bit
Timer 2 write
control bit
“ 0 0 ” , “ 0 1 ” , “ 1 0 ”
“ 1 1 ”
D a t a b u s
3822 Group
Timer 3
interrupt
request
Timer Y
interrupt
request
T i m e r 2
i n t e r r u p t
r e q u e s t
Timer 1
interrupt
request
C N T R
i n t e r r u p t
r e q u e s t
Timer X
interrupt
request
CNTR
interrupt
request
0
1
25

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