M38227ECFP Renesas Electronics America, M38227ECFP Datasheet - Page 37
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M38227ECFP
Manufacturer Part Number
M38227ECFP
Description
IC 740 MCU EPROM 48K 80QFP
Manufacturer
Renesas Electronics America
Series
740/38000r
Datasheet
1.M38227ECFP.pdf
(82 pages)
Specifications of M38227ECFP
Core Processor
740
Core Size
8-Bit
Speed
8MHz
Connectivity
SIO, UART/USART
Peripherals
LCD
Number Of I /o
49
Program Memory Size
48KB (48K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M38227ECFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M38227ECFP
Manufacturer:
MIT
Quantity:
20 000
Company:
Part Number:
M38227ECFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M38227ECFP#U0
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD
Fig. 32 Structure of segment output enable register and LCD mode register
34
Segment output enable register
LCD display RAM
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
b 7
b 7
N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r .
b 0
b 0
L C D m o d e r e g i s t e r
( L M : a d d r e s s 0 0 3 9
Segment output enable register
(SEG : address 0038
Segment output enable bit 0
Segment output enable bit 1
Segment output enable bit 2
Segment output enable bit 3
Segment output enable bit 4
Segment output enable bit 5
Not used (returns “0” when read)
Duty ratio selection bits
Bias control bit
LCD enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
LCDCK count source selection bit (Note)
Table 11 Maximum number of display pixels at each duty ratio
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
(Do not write
0 0 : Not used
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
0 : 1/3 bias
1 : 1/2 bias
0 : LCD OFF
1 : LCD ON
0 : Input port P3
1 : Segment output SEG
0 : I/O port P0
1 : Segment output SEG
0 : I/O port P0
1 : Segment output SEG
0 : I/O port P1
1 : Segment output SEG
0 : I/O port P1
1 : Segment output SEG
0 : I/O port P1
1 : Segment output SEG
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
0 : f(X
1 : f(X
Duty ratio
mode)
2
3
4
CIN
IN
)/8192 (or f(X
)/32
“1”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
to this bit.)
0
2
0
2
3
1 6
,P0
–P0
,P1
–P1
4
)
0
0
0
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
–P3
, COM
–COM
–COM
16
1
1
7
7
)
7
CIN
MITSUBISHI MICROCOMPUTERS
)/8192 in low-speed
Maximum number of display pixel
1
2
3
12
16
18
24
26
27
)
)
)
–SEG
, SEG
–SEG
, SEG
–SEG
15
17
23
25
31
3822 Group