D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 343

• Manufacturer Part Number: D12363VF33V
• Description: IC H8S/2363 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
7.5.13
When the DMAC accesses external space, conflict with a refresh cycle or external bus release
cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle
or external bus release cycle, in accordance with the external bus priority order, even if the DMAC
is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has
a lower priority than the DMAC, is not executed until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
Relation between DMAC and External Bus Requests and Refresh Cycles
RD
φ
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.34 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Rev.6.00 Mar. 18, 2009 Page 283 of 980
Idle
Section 7 DMA Controller (DMAC)
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
REJ09B0050-0600
DMA write
Read
DMA
read