D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 890

• Manufacturer Part Number: D12363VF33V
• Description: IC H8S/2363 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Power-Down Modes
23.2
23.2.1
When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to
clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the operating clock (1/2 or 1/4) specified by bits SCK2
to SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
23.2.2
Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in
SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of
the CPU’s internal registers are retained. Other peripheral functions do not stop.
Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
• Exiting Sleep Mode by Interrupts:
• Exiting Sleep Mode by RES pin:
• Exiting Sleep Mode by STBY Pin:
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When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception processing.
Clock Division Mode
Sleep Mode
Operation