D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 572

• Manufacturer Part Number: D12363VF33V
• Description: IC H8S/2363 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 8-Bit Timers (TMR)
Table 12.2 Clock Input to TCNT and Count Condition
Channel
TMR_0
TMR_1
All
Note:
12.3.5
TCSR displays status flags, and controls compare match output.
TCSR_0
Rev.6.00 Mar. 18, 2009 Page 512 of 980
REJ09B0050-0600
Bit
7
*
Bit Name
CMFB
Timer Control/Status Register (TCSR)
If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
Bit 2
CKS2
0
1
0
1
1
TCR
Bit 1
CKS1
0
1
0
0
1
0
0
1
1
Initial Value
0
Bit 0
CKS0
0
1
0
1
0
0
1
0
1
0
1
0
1
R/W
R/(W) *
Description
Clock input disabled
Internal clock, counted at falling edge of φ/8
Internal clock, counted at falling edge of φ/64
Internal clock, counted at falling edge of φ/8192
Count at TCNT_1 overflow signal *
Clock input disabled
Internal clock, counted at falling edge of φ/8
Internal clock, counted at falling edge of φ/64
Internal clock, counted at falling edge of φ/8192
Count at TCNT_0 compare match A *
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
Description
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
•
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0