M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 205

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 14.9 U2SMR3 and U2SMR4 Registers
6
0
1
C
9
1 .
B
2 /
0
2
9
1
M
NOTE:
UART2 Special Mode Register 4
0
UART2 Special Mode Register 3
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
G
1
r a
1. Set to 0 when each condition is generated.
0 -
o r
3 .
1. Bits DL2 to DL0 are used to generate a delay in SDA output by digital means during I
2. The amount of delay varies with the load on pins SCL2 and SDA2. Also, when using an external clock, the amount of
1
u
, 0
1
mode,set these bits to 000
delay increases by about 100 ns.
p
2
2
0
0
7
page 179
RSTAREQ
STSPSEL
Symbol
STAREQ
STPREQ
CKPH
NODC
Symbol
(b0)
(b2)
(b4)
DL0
DL1
DL2
SCLHI
SWC9
ACKD
ACKC
Bit
Bit
2
f o
(no delay).
Symbol
U2SMR4
Symbol
U2SMR3
4
5
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Clock phase set bit
Clock output select bit
SDA
setup bit
(1, 2)
8
Start condition
generate bit
Restart condition
generate bit
Stop condition
generate bit
SCL
select bit
ACK data bit
ACK data output
enable bit
SCL
enable bit
SCL
2
digital delay
2
2
2
Bit Name
,SDA
output stop
wait bit 3
Bit Name
2
(1)
Address
0374
output
(1)
(1)
Address
0375
16
16
b7 b6 b5
0 : Without clock delay
1 : With clock delay
0 : CLK
1 : CLK
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of U2BRG count source
0 1 0 : 2 to 3 cycles of U2BRG count source
0 1 1 : 3 to 4 cycles of U2BRG count source
1 0 0 : 4 to 5 cycles of U2BRG count source
1 0 1 : 5 to 6 cycles of U2BRG count source
1 1 0 : 6 to 7 cycles of U2BRG count source
1 1 1 : 7 to 8 cycles of U2BRG count source
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
0 : Disabled
1 : Enabled
0 : SCL
1 : SCL
After Reset
00
2
2
16
is CMOS output
is N-channel open drain output
2
2
After Reset
000X0X0X
“L” hold disabled
“L” hold enabled
Function
Function
2
2
C bus mode. In other than I
2
C bus
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
14. Serial I/O