M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 373

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
20.7 Software Commands
e
E
1
. v
J
Table 20.5 Software Commands
6
0
SRD: Status register data (D
WA : Write address (However,even address)
WD : Write data (16 bits)
BA : Highest-order block address (However,even address)
xx : 8 high-order bits of command code (ignored)
Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a
command code, 8 high-order bits (D
X : Any even address in the user ROM area
20.7.1 Read Array Command (FF
20.7.2 Read Status Register Command (70
20.7.3 Clear Status Register Command (50
1
9
C
Read array
Read status register
Clear status register
Block erase
Program
1 .
B
2 /
The read array command reads the flash memory.
Read array mode is entered by writing command code xxFF
fied address can be read in 16-bit unit after the next bus cycle. The MCU remains in read array mode until
an another command is written. Therefore, contents of multiple addresses can be read consecutively.
The read status register command reads the status register.
By writing command code xx70
cycle (Refer to 20.8 Status Register). Read an even address in the user ROM area. Do not execute this
command in EW mode 1.
The clear status register command clears the status register to 0.
By writing xx50
SR5 in the status register are set to 0.
0
2
9
1
M
0
G
1
r a
0 -
o r
Command
3 .
1
u
, 0
1
p
2
2
0
0
7
16
page 347
in the first bus cycle, and bits FMR06 to FMR07 in the FMR0 register and bits SR4 to
7
to D
f o
Mode
Write
Write
Write
Write
Write
0
4
)
5
16
8
in the first bus cycle, the status register can be read in the second bus
15
–D
First bus cycle
8
Address
) are ignored.
16
WA
)
X
X
X
X
(D
16
16
xxFF
xx70
xx50
xx40
xx20
15
Data
)
)
to D
16
16
16
16
16
0
16
)
in the first bus cycle. Content of a speci-
Mode
Write
Write
Read
Second bus cycle
Address
WA
BA
X
(D
xxD0
15
SRD
Data
WD
to D
16
0
)