M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 489

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.10
10/10/06
Date
REVISION HISTORY
133 to 138 Figure 13.1 to 13.6 are partly revised.
All Pages Package code changed: 80P6Q-A to PLQP0080KB-A, 64P6Q-A to PLQP0064KB-A
253,254 Figure 16.6 and Figure 16.7 are partly revised.
367,368 “21.2 Memory Map” is partly revised.
391,392 Figure 21.9.1 and Figure 21.9.2 are partly revised.
393,394 Figure 21.9.2.1 and Figure 21.9.2.2 are partly revised.
397,398 Figure 21.11.1 and Figure 21.11.2 are partly revised.
80, 81
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“9.3 Interrupt Control” is partly revised.
“9.6 INT Interrupt” and “9.7 NMI Interrupt” are partly revised.
“9.8 Key Input Interrupt” and “9.9 CAN0 Wake-up Interrupt” are partly revised.
“10. Watchdog Timer” is partly revised.
“10.1 Count source protective mode” is partly revised.
Note 2 in Figure 10.2 is revised.
Figure 12.3.1 is partly revised.
“Three-phase output buffer register” in Figure 12.3.4 is partly revised.
“Function enable register” in Figure 13.9 is partly revised.
Table 13.4.1 is partly revised.
“13.6 I/O Port Function Select” is partly revised.
Figure 14.1.4.1 is partly revised.
Figure 14.2.1 is partly revised.
Figure 14.2.2 is partly revised.
“Integral Nonlinearity Error” in Table 15.1 is partly revised.
“16.5.4 Bit 3: Arbitration lost detection flag” is partly revised.
“16.6.5 I2C system clock select bits” and Talbe 16.6 are partly revised.
“9)” in “16.13.2 Example of Slave Receive” is revised.
“17.3 Configuration of the CAN Module System Clock” is partly revised.
“18.1 CRC snoop” is partly revised.
Table 20.25 is partly revised.
“21.1 Flash Memory Performance” is partly revised.
“21.4 CPU Rewrite Mode” is partly revised.
“21.4.1 EW0 Mode” and “21.4.2 EW1 Mode” are partly revised.
“FMR01 Bit” is partly revised.
“FMR17 Bit” is partly revised.
“21.7.4 Program Command (40
Table 21.9.1 and Note 2 are partly revised.
Table 21.11.1 and Note 1 are partly revised.
Figure 21.11.3 is partly revised.
Words standardized: Low voltage detection, CPU clock, MCU, SDA
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C-5
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Description
16
)” is partly revised.
M16C/29 Hardware Manual
Summary
2
, SCL
2